Integrated circuits are liable to damage from electrostatic potential variations, electromagnetic interference (EMI), electrical overstress (EOS), and electrostatic discharge (ESD) during fabrication as well as during normal operation. During fabrication, one source of ESD is charge induced by the various plasma etch and plasma deposition processes. During fabrication, plasma processes can have non-uniform electrical fields and magnetic fields in a semiconductor tooling. Non-uniformities in the electrical field, and the plasma environments can lead to non-uniform charge deposition in a semiconductor wafer. Additionally, these voltage gradients can lead to plasma arcing. Voltage gradients that are established across a semiconductor wafer can lead to charge re-distribution and damage to components on the wafer. After fabrication there are many potential sources of ESD, for example handling of the integrated circuit chips. A related type of ESD-like damage can occur between various sub-circuits and structures operating at different voltage levels during normal operation of the integrated circuit. Similarly electromagnetic induced (EMI) cross-talk between various circuits and structures during normal operations can cause damage to as well as failures of the integrated circuit.
Therefore, there is a need for a method and structure for charge dissipation during fabrication of integrated circuits and isolation of circuits and structures in completed integrated circuits.